The present invention relates to a semiconductor device, and particularly to a semiconductor integrated circuit device, hereinafter referred to as an IC, having a plurality of bonding pads formed on a semiconductor chip.
Semiconductor devices in general have a construction in which a semiconductor chip is secured onto a lead frame, and the external leads and the semiconductor chip are electrically connected together via wires having good electrical conductivity such as gold wires.
The region for connecting the wire in the semiconductor chip is called the bonding pad and is usually obtained by forming a layer of metal such as aluminum on an oxide film covering the surface of a semiconductor substrate, and forming an aperture in a portion of a final passivation film that covers the metal layer, such that the surface of a portion of the metal layer is exposed.
As is well known, the electric connection (bondability) between the bonding pad and the wire is an important parameter that greatly affects the characteristics of the semiconductor device. A variety of wire-bonding methods have been developed to obtain good connection between the two. However, all of such methods contain a scrubbing step in which the tip of wire and the bonding pad are strongly scrubbed relative to each other.
The thickness of the oxide film on the surface of the semiconductor substrate has decreased as the size of modern semiconductor devices has decreased. Therefore, if a load is applied to the wire and the bonding pad is scrubbed by the wire in the scrubbing step contained in the step of wire bonding, the pressure is transmitted to a thin oxide film which covers the surface of the semiconductor substrate under the bonding pad, so that the oxide film is destroyed or pinholes are formed.
Development of such defects substantially short-circuits the wire and the semiconductor substrate so that the signals are not effectively transmitted to the elements formed in the semiconductor substrate.
Japanese Patent Publication No. 25466/1971 proposes a solution to the above-mentioned problem, as shown in FIG. 19. Namely, a silicon n.sup.- -layer 4 is epitaxially grown on a single crystalline silicon p.sup.- -substrate 1. The silicon n.sup.- -layer is electrically isolated by p-isolation layers 8 into several semiconductor island regions in which will be formed elements such as transistors. An aluminum electrode (wiring) 16 connected to these elements is connected to a bonding pad 2 in the vicinity of the chip (substrate), and a wire 19 is bonded between the bonding pad 2 and an external lead, thereby constituting an IC. The bonding pad 2 is formed on an SiO.sub.2 film 10 which is an insulating film on the surface of the silicon layer 4. If pinholes exist in the SiO.sub.2 film under the bonding pad, a leakage current flows into the semiconductor layer 4 through pinholes to adversely affect the circuits that constitute an IC. In order to prevent such a leakage current from flowing, the above-mentioned literature discloses an art according to which a p-isolation layer 8 is formed under the periphery of the pad as shown in FIG. 19, and the isolation layer 8 is maintained at the smallest operating potential so that the n.sup.- -layer 4a just under the bonding pad is an electrically floating island. With the thus constructed device, even if a defect B develops in the oxide film 10 under the bonding pad as shown in FIG. 19, and the pad and the n.sup.- -semiconductor layer 4a are short-circuited relative to each other, the signal is not allowed to flow into the semiconductor substrate but is effectively transmitted to a predetermined element region. The inventors of the present invention have studied the above technique extensively. FIG. 20 is a diagram showing the layout of a portion of an IC that was described by the inventors of the present invention based on the assumption that the device of FIG. 19 is embodied as a practical IC.
A common p-isolation layer 8a surrounds n.sup.- -layers 4a just under a plurality of pads 2a, 2b arranged close to a scribe region 24 in the peripheral portion of the semiconductor chip, and the isolation layer 8 is maintained at ground potential. The n.sup.- -layers 4a are floating islands which are surrounded by the isolation layer 8a. Reference numeral 4b denotes regions where there will be formed elements, such as npn-transistors, pnp-transistors, and diodes. The individual elements are isolated by an isolation layer 8b. All the regions 4b where elements are formed, are electrically isolated from other regions 4a, 4c. Reference nuneral 5 denotes a p-diffusion resistance layer that is formed on the surface of a region 4c which consists of an n.sup.- -layer.
According to the study conducted by the inventors, peripheries of a plurality of pads are surrounded by the isolation layer 8a and, therefore, become dead space that cannot be used for forming elements. Furthermore, some space that exists among the pads must be filled with the isolation layer, imposing a limitation on increasing the density of integration.
Further, when there are several island regions consisting of diffusion resistances 5 as shown in FIG. 20, a power source contact must be provided for each of the island regions so that the power source potential Vcc is applied to the epitaxial n.sup.- -layers 4c that serve as island regions where the resistance will be formed. This restricts the freedom of wiring.